We have included here a glossary section to try and explain some of the techno-jargon which you may come across either on our website or any other technical websites you may from time to time visit.
| ABV | Assertion Based Verification |
| AMBA | Advanced Microcontroller Bus Architecture; an open standard, on-chip bus specification that serves as a framework for SoC designs. |
| APB | Advanced Peripheral Bus; one of the basic AMBA interface standard buses specifically optimised for low-power peripherals. |
| AHB | Advanced High-performance Bus; one of the more advanced AMBA interface standard buses. There is a fully featured version and also a scaled-down “Lite” version available. |
| ASIC | Application Specific Integrated Circuit; is an Integrated Circuit which is customized for a specific use rather than intended for general-purpose use. |
| ASM | Algorithmic State Machine; a method for describing finite state machines. |
| Assertion | An assertion is style of property used by a designer or verification engineer to describe design intent. This can describe either legal or illegal behaviour of a circuit and is used as part of an ABV flow. |
| Assumption | An assumption is style of property used by a designer or verification engineer to describe expected design conditions or inputs. This is used as part of an ABV flow. Within a simulation-based flow, an assumption will produce an error if it is triggered. Within a Formal Verification-based flow, as assumption is used by the formal engine to reduce the state space explored. |
| Autochecks | An series of automatic design checks which are used to determine the quality of a design. These will normally include CDC, Deadlock, Deadcode, Reset propagation and tri-state contention, amongst others. |
| AXI | Advanced eXtensible Interface; the most recent AMBA interface standard bus. |
| Behavioral | A level of logic design that involves describing a system at a level of abstraction which does not involve circuit elements, but instead describes functionality as equations or descriptions. This is a much higher level of abstraction than RTL level. |
| CDC | Clock Domain Crossing; when a signal crosses from one clock domain to another. If a signal does not assert for long enough or is not registered it may appear asynchronous at the receiving clocked logic, due to violation of setup or hold times. This can cause metastability. |
| Core | An alternate name for a piece of IP. |
| CPLD | Complex Programmable Logic Device |
| EDA | Electronic Design Automation; refers to software tools which are used in the design and development of electronic devices and systems |
| EDIF | Electronic Design Interchange Format; an industry-standard netlist format. This is normally used to pass information from Synthesis tools to P&R tools |
| ESL | Electronic System Level; this is a loosely defined and still emerging realm of chip development. Work is done at a higher level of abstraction to concentrate more on the overall system functionality than the implementation details of the hardware. Interfaces at this level are normally expressed using TLM. |
| Formal Verification | The method for proving or disproving the correctness of a design with respect to a series of properties using formal mathematical methods. |
| FPGA | Field Programmable Gate Array |
| FSM | Finite State Machine; often just called a "state machine", is a model of behaviour composed of a finite number of states, transitions between these states, and actions. One form is the "Moore machine", where the output is only determined by the current state. Another form is the "Mealy machine", where the output is determined by both the current state and its inputs. |
| HDL | Hardware Description Language; a textual means of representing a piece of hardware, normally referred to as "code". This is normally Simulated to check functionality or Synthesized to produce hardware. The two most widely used HDLs are VHDL and Verilog. |
| IBD | Interface Based Design; a tabular interconnect methodology used within the HDL Designer Series product as an alterative to Block Diagrams. |
| IP | Intellectual Property; a pre-written function in an HDL language or EDIF netlist that can be incorporated into a design meaning it does not have to be written or verified by the end user. |
| LRM | Language Reference Manual; Copies of these can be purchased and used for reference purposes from shop.ieee.org . |
| P&R, PAR | Place and Route; the process by which an FPGA/CPLD/ASIC vendor maps logic onto the physical logic and routing elements on the target silicon. |
| PCB | Printed Circuit Board; a board upon which electronic components are mounted and connected together using copper tracks. |
| Physical Synthesis | This is where the synthesis flow makes use of its knowledge of the physical layout and timing of the target device in order to achieve the minimum area usage at the required speed. |
| Property | A machine readable description of some aspect of your designs intended functionality |
| PSL | Property Specification Language; a language developed by Accellera for specifying properties or assertions about hardware designs. These can either be used with Simulation or Formal Verification. |
| PWB | Printed Wiring Board; an alternate name for a PCB. |
| RTL | Register Transfer Level; this is quite a low level of abstraction where logic is described in terms of sequential and combinational logic using languages such as VHDL or Verilog. This is a much lower level of abstraction than behavioral-level. |
| Simulation | Using software programs to allow the functionality of RTL code to be modelled. A series of test vectors are applied to the model and the results can then be displayed or used to check for functionality and timing. |
| SoC | System-on-a-Chip/System-on-Chip; the combination of several, often disparate, associated functions on one single chip. |
| SSTA | Statistical Static Timing Analysis |
| SVA | SystemVerilog Assertions; - see www.ieee.org . |
| Synthesis | The process which takes RTL code and converts this into a Hardware implementation. There are a number of restrictions to this and so not all code which may be Simulated (see Simulation), may be Synthesized. |
| SystemC | This is a system description language originally developed by Synopsys Inc. |
| SystemVerilog | An extension of the Verilog language which supports Assertions, TestBench Automation, Coverage checks and TLM. IEEE 1800-2005 - see www.ieee.org . |
| TLM | Transaction Level Modelling, an abstraction used to explore different design architectures without the overhead of designing or simulating the details of how particular transforms may be implemented. |
| Verilog | One of the 2 dominant HDL languages for FPGA/ASIC design. IEEE 1364-1995 and 1364-2001 - see www.ieee.org . |
| VHDL | VHSIC (Very High Speed Integrated Circuit) Hardware Description Language; One of the 2 dominant HDL languages for FPGA/ASIC design. IEEE 1076-1987, 1076-1994, 1076-2002 - see www.ieee.org . |